Operational unit



Nov. 10, 1970 TOSHI'YUKI MATsuDAi 3,539,935

OPERATIONAL UNIT Filed on. 22, 1968 5 Sheets-Sheet 1 Rf Zf I II -Rf RiRI Zi R-O- IO R0 Rf+Ri INVENTOR I TOSHIYUKI MATSUDA ATTORNEY 10, 1970TOSHIYUKI MATsuDA 3,53,

OPERATIONAL UNIT Filed Oct. 22, 1968 3 Sheets-Sheet 2 +E L Rl 2 Rf C A RR i} |Ii I 1 01 [{JfR INVENTOR TOSHIYUKI MATSUDA BY 7 I '1 ATTORNEYUnited States Patent 3,539,935 OPERATIONAL UNIT Toshiyuki Matsuda,Tokyo, Japan, assignor to Honeywell Inc., Minneapolis, Minn., acorporation of Delaware Filed Oct. 22, 1968, Ser. No. 769,640 Claimspriority, application Jzapan, Oct. 27, 1967,

,8 Int. Cl. H0315 1/02, 1/38 US. Cl. 330-9 1 Claim ABSTRACT OF THEDISCLOSURE BACKGROUND OF THE INVENTION This invention relates to anoperational unit usable in industrial electronic control devices.

SUMMARY OF THE INVENTION In the invention of subject application, anoperational unit having a current input and a current output comprises;an input current source having an output terminal connected to a firstreference potential line; an operational input resistance connectedbetween another output terminal of the input current source and a secondreference potential line having a voltage higher than that of the firstreference potential line; a high gain operational amplifier having oneof a pair of input terminals connected to the second reference potentialline; an operational circuit consisting of a first operational impedanceconnected between one end of the operational input resistance and theother input terminal of the operational amplifier, and a secondoperational impedance having one end thereof connected to the otherinput terminal of the operational amplifier; an output current sourcehaving one output terminal connected to a third reference potential linehaving a voltage higher than that of the second reference potential lineand adapted to generate a curent signal corresponding to an output fromthe operational amplifier under the control of the output from theoperational amplifier; a first transistor having an emitter thereofconnected to another output terminal of the output current sourcethrough an operational output resistance, a base thereof connected tothe second reference potential line, and a collector thereof connectedto one end of a load having the opposite end thereof connected to thefirst reference potential line; a second transistor having a base therofconnected to a joint between the output resistance and the outputcurrent source, a collector thereof-connected to the third referencepotential line, and an emitter thereof connected to the operationalcircuit; an output circuit consisting of the first and the secondtransistors; and a bias current source having an output terminalconnected to the third reference potential line and another outputterminal connected to the other terminal of the input current source.

Therefore, a principal object of the present invention is to provide anoperational unit having a current input and a current output.

"ice

Another object of the present invention is to provide an operationalunit of the type fulfilling the aforesaid principal object, in which theoutput current is not affected by load variation and the negativefeedback voltage is not influenced by temperature variation.

A further object of the present invention is to provide a noveloperational unit capable of carrying out various mathematical operationssimply by adding or removing suitable constituent elements.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electric circuit diagramof a mathematical operational unit provided in accordance with thepresent invention;

FIG. 2 is a block diagram showing transfer functions of the operationalunit of FIG. 1;

FIG. 3 is a circuit diagram of an embodiment of the time delay circuitprovided according to the present invention;

FIG. 4 is a circuit diagram of an embodiment of the differentiatorprovided according to the present invention; and

FIG. 5 is a circuit diagram of an embodiment of the integrator providedaccording to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, 1 represents a firstreference potential line, e.g., a ground potential line, 1 a secondreference potential line, e.g.,a +12 Volt DC. line, and l a thirdreference potential line, e.g., a }-E volt (for instance, +24 volt) D.C.line The symbol A designates a high gain operational amplifier havingone of the pair of input terminals connected to a connecting point 5 onthe second reference potential line l and the other input terminal toanother connecting point 4, respectively. Z and Z are a first and asecond operational impedance connected to connecting point 4 at one endthereof, respectively. R is an operational input resistance connectedbetween the second reference potential line 1 and a connecting point 2directly joined with an input terminal 1 of the operational unit. Theopposite end of the first operational impedance Z, is connected toconnecting point 2. An input current source CCS is connected betweeninput terminal 1 of the operational unit and the first referencepotential line l The voltages of the third and of the second referencepotential lines 1 and 1 are fed to the operational amplifier A throughlead wires and I respectively. An operational circuit is formed by acombination of the operational amplifier A, the operational inputresistance Ry and the first and the second operational impedances Z andZ An output current sources CCS generates an output current Icorresponding to an output 16 from the operational amplifier A, or theoutput from the operational circuit, and one of the pair of outputterminals of the output current source connected to the third referencepotential line 1 while the other output terminal thereof to a connectingpoint 14, respectively. An operational output resistance R has one endthereof connected to connecting point 14, or to the other outputterminal of the output current source CCS A first transistor Q which isused as an impedance converter circuit, has a base connected to thesecond reference potential line 1 and an emitter connected to the otherend of the operational output resistance R.,. A load R is connectedbetween a collector of the first transistor Q and the first referencepotential line 1 In other words, the load R is connected to the outputcurrent source CCS through the impedance converter circuit and theoperational output resistance R A second transistor Q of the outputcircuit generates feedback signals (a voltage V and a current I whichaccurately correspond to the output current I and provides means forfeeding feedback signals to the operational circuit. The secondtransistor Q has a base connected to connecting point 14, a collectorconnected to the third reference potential line 1 and an emitterconnected to one end of an operational feedback resistance R, has theopposite end thereof connected to connecting point 2. The emitter of thesecond transistor Q is further connected to one end of the secondoperational impedance Z; through a bias voltage source E In theparticular embodiment, illustrated in FIG. 1, the bias voltage source Ecomprises a constant-voltage diode D a resistance R and a potentiometerR shunting the diode D in which the diode D and the resistance R areconnected in series with each other and inserted between the emitter ofthe second transistor Q and the first reference potential line 1Accordingly, the one end of the second operational impedance Z: isconnected to a sliding terminal of the potentiometer R A constantvoltage circuit for providing a constant voltage to the second referencepotential line 1 consists of a constant voltage diode D and a resistanceR in which the diode D is connected between the first referencepotential line 1 and the second reference potential line 1 while theresistance R is connected between the second reference potential line 1and the third reference potential line 1 A bias current source CCS isinserted between the third reference potential line 1 and input terminal1 of the operational unit, to feed a bias current I to the operationalunit.

The first transistor Q, is of a PNP type, while the second transistor isof an opposite NPN type, and both the first and the second transistorsshould preferably have a high gain. Those skilled in the art can easilyconceive of a composite transistor of complementary connection and thelike can be also used, depending on the case.

The operational amplifier A is a so-called negative high gain amplifier,and its operation is such that the output current I from the outputcurrent source CCS increases when the input voltage thereto is reduced.The magnitude of the output current I from the output current source CCScorresponds to the output signal from the operational amplifier A, andsuch output current source can be constructed by using a knowntransistor circuit, as apparent to those skilled in the art.

The operation of the circuit of FIG. 1 will now be described. Forsimplicity it is assumed the bias current and the bias voltage are nil,or 1 :0 and E =0.

When the output current source CCS generates an output current 1corresponding to the output from the operational amplifier A of theoperational circuit, the output current 1 is fed to the first transistorQ through the operational output resistance R Since the first transistorQ is in the form of the so-called base grounded transistor amplifiercircuit with the base thereof connected to the second referencepotential line 1 the almost entire current in the resistance R is fed tothe load R through the emitter and the collector of the transistor Q. Aswill be described hereinafter, the current flowing into the secondtransistor Q is negligibly small, and hence, the output current -I flowsthrough the load R As described above, the second transistor Q has abase connected to connecting point 14, a collector connected to thethird reference potential line 1 and a emitter connected to the secondreference potential line l through the resistances R, and R in series,and accordingly, it forms a transistor amplifier of emitter followerconnection, in which the input is the voltage drop (l R -l- V betweenconnecting point 14 and the second reference potential line 1 The seriesconnected resistances (R +R form a feedback resistance of the transistoramplifier. The negative feedback voltage V of the second transistor Qwhich appears between the emitter of the transistor Q and the secondreference potential line 1 is given-by the following equation.

f o o+( be1 be2) Here, V and V are base-emitter voltages of the firstand the second transistors Q and Q respectively. Such base-emitterVoltages vary responsive to the ambient temperature variation, but inthe particular circuit of FIG. 1, those base-emitter voltages of thetransistors Q and Q are cancelled with each other, as shown by theEquation 1. As a result of it, by selecting the transistors Q and Q ofsuitable voltage drop characteristics, the term (V V can be madenegligibly small. Thus, the Equation 1 can be simplified as shown by thefollowing Equation 2.

According to the Equation 2, the negative feedback voltage V accuratelycorresponds to the output current I and it is not affected at all by anychange in the baseemitter voltages of the transistors due to ambienttemperature variations.

The magnitude of the negative feedback current I; passing through theresistance R will now be determined. An input current I, to theoperational unit is 'fed from the input current source CCS through theresistance R which flows in the direction from the second referencepotential line l to connecting point 2. The negative feedback cur rentI; fiows from the emitter of the transistor Q to connecting point 2.Accordingly, the following Equation 3 can be derived.

r rx r) 1+ bei o o+ be2 By solving the Equation 3 for I r= 1 1 1-ir)+ oo r'ir)+( be2 bel) As explained above, the term (Vb 2'Vb 1) can be madenegligibly small by selecting proper transistors Q and Q Thus, theEquation 4 can be simplified to the following Equation 5, which showsthat the negative feedback current I is not affected by the ambienttemperature variation.

The input voltage V, to the operational circuit is the I= 1 1 i+ r)+ o o1+ r) voltage drop across the operational input resistance R which isgiven by the product of the resistance value R; and the differencecurrent (I I between the input current I, and the negative feedbackcurrent I The input voltage V, is applied to the input terminals of theoperational amplifier A through the first operational impedance 2,,while the negative feedback voltage V, is applied to the input terminalsof the operational amplifier A through the second operational impedanceZf- As well known in the art, the operational circuit carries out themathematical operation defined by the following Equation 6.

By substituting the Equation 5 defining 1,,

and V =I R into the Equation 6, and by rearranging, the

following Equation 7 can be derived to describe the relation between theinput current I, and the output current I r o)( r 1)( 1 1+ r)) 1 1 1+r))( r 1)) o Therefore, the transfer function of the operational unit,

according to the present invention, can be given the following Equation8.

O r r/ i)( i/( i+R:)) i 0 f/ i)( i/( i+ t)) FIG. 2 shows a blockdiagramof the transfer function of the operational unit of the presentinvention, as expressed in the Equation 8, in which each blockrepresents the corresponding term of the Equation 8 and the blocks areso assembled as to satisfy the relation'. of the Equation 8. As depictedin FIG. 2 and expressed in the Equation 8, the operational unitaccording to the present invention includes not only afundamentaloperation circuit having a transfer function of Z /Z but alsoother operational factors having transfer functions R (RH-R R l/R andR,,/(R +R respectively. Thereby, a variety of different mathematicaloperations can be carried out Here,

/R1, and

S=jw, 0.! being the angular frequency of the input current 1,.

FIG. 4 shows a circuit diagram of a diiferentiator according to thepresent invention, which is similar to the circuit of FIG. 1, exceptthat the bias current source CCS is eliminated, while substituting acapacitor C and a variable resistance R for the first operationalimpedance Z; and the second operational impedance Z; of FIG. 1,respectively. The following Equation 10 represents the transfer functionfor the dilferentiator of FIG. 4.

Here,

FIG. 5 shows a circuit diagram of an integrator according to the presentinvention, which is similar to the circuit of FIG. 1 except that theoperation feedback ressitance R; of FIG. 1 is eliminated, whilesubstituting a resistance R and a capacitance C for the firstoperational impedance Z; and the second operational impedance Z of FIG.1, respectively. Furthermore, in the circuit of FIG. 5, a switch K isinserted between a connecting point 4 and the sliding element of apotentiometer R and one end of the capacitor C is connected to theemitter of a second transistor Q The Equation 11 gives the transferfunction F(s) for the integrator of FIG. 5.

Here,

T (R /RQRC, and S=fw As described in the foregoing, according to thepresent invention, there is provided an operational unit comprising anoperational circuit including a high gain operational amplifier A, anoperational input resistance R a first operational impedance 2,, and asecond operational impedance Z an output current source CCS forgenerating an output current corresponding to the output from theoperational amplifier A; an impedance converter circuit including a basegrounded type transistor Q1; a negative feedback means including anothertransistor Q having a polarity opposite to that of the transistor Q andadapted to generate a negative feedback voltage accurately correspondingto an output current I for applying the thus generated negative feedbackvoltage to said operational circuit; means R connected between thenegative feedback means and an input terminal of the operationalamplifier, and adapted to feed a negative feedback current to saidoperational circuit, said negative feedback current being related to aninput current I, and the output current I of the operational circuit;and an output circuit consisting of said negative feedback means and themeans R,. The impedance converter circuit is made of base grounded typetransistor circuit, hence, the input impedance thereof is low while theoutput impedance thereof is very high. Accordingly, the output current Idelivered to the load through such impedance converter circuit is notaffected by the load variation. It should be noted as another feature ofthe present invention that a negative feedback means including a firsttransistor and a second transistor having opposite polarities to eachother is used, in conjunction with the aforesaid transistor typeimpedance converter circuit, so that the base-emitter voltages V of thetwo transistors are cancelled with each other. Thus, the negativefeedback voltage accurately represents the output current I In addition,such negative feedback voltage is not affected by the temperaturevariation. Besides, by adopting such circuit construction, in which notonly the negative feedback voltage V, but also the negative feed backcurrent I: are fed back to the operational circuit, a variety ofdifferent mathematical operations can be carried out by the operationalunit, as shown by the Equation 8. For example, FIGS. 3 to 5 illustratedifferent operational units for different mathematical operations. Informing such different operational units, the number of circuit elementsor parts is not increased, and such circuit construction can becompleted simply by replacing a few circuit elements or reconnectingthem. In other words, the modification can be made very easily.

Another feature of the operational unit according to the presentinvention is in that the common line or the second reference potentialline is separated from the power source lines l and I so that onlysignal currents I and I; (which are in the order of severalmilliaimperes to several ten milliamperes, as well known in the art)flows through the common line 1 without allowing passage of unnecessarycurrents therethrough, to suppress the voltage drop in the line 1 causedby such signal currents to a negligibly low level. Thus, in spite of thefact that the operational unit of the present invention is driven by asingle feeder line (in case of FIG. 1, the first and third referencepotential lines l and the influence of the error voltages generatedacross the resistances of the lead wires on the operationalcharacteristics of the unit is negligibly small.

I claim:

1. An operational unit comprising an operational circuit consisting of afirst reference potential line, a second reference potential line havinga voltage higher than that of said first reference potential line, athird potential line having a voltage higher than that of said secondreference potential line, a high gain operational amplifier having aninput terminal connected to said second reference potential line, anoperational input resistance connected between an input terminal of theoperational unit and said second reference potential line, a firstoperational impedance connected between the input terminal of theoperational unit and the other input terminal of said operationalamplifier, and a second operational impedance having one end thereofconnected to the other input terminal of said operational amplifier andthe opposite end thereof so connected as to receive a negative feedbackvoltage; an input current source connected between the input terminal ofthe operational unit and the first reference potential line; a biascurrent source connected between the input terminal of the operationalunit and said third reference potential line; and an output circuit;said output circuit comprising negative feedback means and anoperational feedback resistance, said output circuit consisting of anoutput current source responsive to output signal from said operationalamplifier for gencrating an output current corresponding to the outputfrom said operational amplifier, an impedance converter circuitincluding :a first transistor having a base thereof connected to saidsecond reference potential line, an emitter thereof connected to anoutput terminal of said output current source through an operationaloutput resistance and a collector thereof connected to a load,-anegative feedback means including a second transistor of the oppositepolarity to that of said first transistor and having a collector thereofconnected to said third 6 reference potential line, a base thereofconnected to'said output terminal of said output current source and anemitter thereof connected to the other end of said second ReferencesCited UNITED STATES PATENTS 3,328,713 6/1967 Sukehiroita et a1. 330-18 XNATHAN KAUFMAN, Primary Examiner US. Cl. X.R. 33026, 24

